242 #define PROM_WD_TRIGGER_SCI 0x01 243 #define PROM_WD_TRIGGER_NMI 0x02 244 #define PROM_WD_TRIGGER_SMI 0x04 245 #define PROM_WD_TRIGGER_RESET 0x08 246 #define PROM_WD_WDI_ASSERT_FALLING_EDGE 0x10 247 #define PROM_WD_WDO_TRIGGERED_EARLY 0x20 248 #define PROM_WD_ENABLE_WDI_ASSERTION 0x40 274 #define DE_HW_FAILURE 1 275 #define DE_SW_FAILURE 2 276 #define DE_HW_NOT_SUPPORTED 3 277 #define DE_SW_NOT_SUPPORTED 4 278 #define DE_INVALID_PARM 5 279 #define DE_ALTERNATE_IN_PROGRESS 6 280 #define DE_NONE_IN_PROGRESS 7 281 #define DE_BUFFER_ROLLOVER 8 282 #define DE_ALREADY_PAUSED 10 283 #define DE_OVERFLOW 11 284 #define DE_INVALID_FUNC 12 285 #define DE_DSCUDH_INVALID 13 286 #define DE_INVALID_BOARD 14 287 #define DE_BOARD_LIMIT_REACHED 15 288 #define DE_BOARD_BUSY 16 289 #define DE_INVALID_WINDRVR_HANDLE 17 290 #define DE_INVALID_WINDRVR_VERSION 18 291 #define DE_BAD_WINDRVR_BOARD_INIT 19 292 #define DE_OPERATION_TIMED_OUT 20 293 #define DE_INVALID_WINDRVR_KP 21 294 #define DE_THREAD_FAILURE 22 295 #define DE_DALI_ERROR 23 912 #define QMM_COUNTER_GROUP_1 1 913 #define QMM_COUNTER_GROUP_2 2 916 #define QMM_SOURCE_E1_TC_NM1 0 917 #define QMM_SOURCE_SRC1 1 918 #define QMM_SOURCE_SRC2 2 919 #define QMM_SOURCE_SRC3 3 920 #define QMM_SOURCE_SRC4 4 921 #define QMM_SOURCE_SRC5 5 922 #define QMM_SOURCE_GATE1 6 923 #define QMM_SOURCE_GATE2 7 924 #define QMM_SOURCE_GATE3 8 925 #define QMM_SOURCE_GATE4 9 926 #define QMM_SOURCE_GATE5 10 927 #define QMM_SOURCE_F1_4MHZ 11 928 #define QMM_SOURCE_F2_400KHZ 12 929 #define QMM_SOURCE_F3_40KHZ 13 930 #define QMM_SOURCE_F4_4KHZ 14 931 #define QMM_SOURCE_F5_400HZ 15 934 #define QMM_TOD_DISABLED 0 935 #define QMM_TOD_DIVIDE_BY_5 1 936 #define QMM_TOD_DIVIDE_BY_6 2 937 #define QMM_TOD_DIVIDE_BY_10 3 940 #define QMM_NO_GATING 0 941 #define QMM_ACTIVE_HIGH_TC_NM1 1 942 #define QMM_ACTIVE_HIGH_LEVEL_GATE_NP1 2 943 #define QMM_ACTIVE_HIGH_LEVEL_GATE_NM1 3 944 #define QMM_ACTIVE_HIGH_LEVEL_GATE_N 4 945 #define QMM_ACTIVE_LOW_LEVEL_GATE_N 5 946 #define QMM_ACTIVE_HIGH_EDGE_GATE_N 6 947 #define QMM_ACTIVE_LOW_EDGE_GATE_N 7 950 #define QMM_INACTIVE_OUTPUT_LOW 0 951 #define QMM_ACTIVE_HIGH_PULSE_ON_TC 1 952 #define QMM_TOGGLE_ON_TC 2 953 #define QMM_INACTIVE_OUTPUT_HIGH 4 954 #define QMM_ACTIVE_LOW_PULSE_ON_TC 5 957 #define QMM_ACTION_NONE 0 958 #define QMM_ACTION_ARM 1 959 #define QMM_ACTION_LOAD 2 960 #define QMM_ACTION_LOAD_AND_ARM 3 961 #define QMM_ACTION_DISARM_AND_SAVE 4 962 #define QMM_ACTION_SAVE 5 963 #define QMM_ACTION_DISARM 6 966 #define QMM_SPECIAL_CLEAR_TOGGLE_OUTPUT 0 967 #define QMM_SPECIAL_SET_TOGGLE_OUTPUT 1 968 #define QMM_SPECIAL_STEP_COUNTER 2 969 #define QMM_SPECIAL_PROGRAM_ALARM 3 972 #define QMM_INTERVAL_1MS_1KHZ 0 973 #define QMM_INTERVAL_10MS_100HZ 1 974 #define QMM_INTERVAL_100MS_10HZ 2 975 #define QMM_INTERVAL_1S_1HZ 3 976 #define QMM_INTERVAL_10S_01HZ 4
BYTE DSCUDAPICALL dscQMMMeasurePeriod(DSCB board, BYTE frequency, FLOAT *period)
BYTE DSCUDAPICALL dscQMMReadHoldRegister(DSCB board, BYTE counter, WORD *value)
BYTE DSCUDAPICALL dscQMMSingleCounterControl(DSCB board, BYTE counter, BYTE action)
BYTE DSCUDAPICALL dscQMMSpecialCounterFunction(DSCB board, DSCQMM_SCF *dscqmmscf)
BYTE DSCUDAPICALL dscQMMSetLoadRegister(DSCB board, BYTE counter, WORD value)
BYTE group1_counter_select
BYTE DSCUDAPICALL dscQMMCounterControl(DSCB board, DSCQMM_MCC *dscqmmmcc, BYTE *status)
BYTE DSCUDAPICALL dscQMMSetCMR(DSCB board, DSCQMM_CMR *dscqmmcmr)
BYTE DSCUDAPICALL dscQMMReset(DSCB board)
BYTE group2_counter_select
BYTE DSCUDAPICALL dscQMMMeasureFrequency(DSCB board, BYTE interval, BYTE source, FLOAT *freq)
BOOL external_gate_enable
BYTE DSCUDAPICALL dscQMMPulseWidthModulation(DSCB board, DSCQMM_PWM *dscqmmpwm)
BYTE DSCUDAPICALL dscQMMSetMMR(DSCB board, DSCQMM_MMR *dscqmmmmr)
BYTE DSCUDAPICALL dscQMMSetHoldRegister(DSCB board, BYTE counter, WORD value)
struct DSCAUTOCAL DSCADCALPARAMS
DSCSAMPLE * sample_values